The present invention relates to a complex logic circuit composed of ECL (emitter coupled logic) circuitry.
ECL (or often CML: current mode logic) circuits can be constructed either as a differential transistor circuit without an emitter follower output circuit, as shown in FIG. 1, or as a differential transistor circuit with an emitter follower output circuit as shown in FIG. 2. The ECL circuit without an emitter follower output circuit and the ECL circuit having an emitter follower output circuit have both been reported in a journal "CIRCUIT DESIGN FOR INTEGRATED ELECTRONICS" by H. R. Camenzind, published by Addison-Wesley Co., 1968, pp. 157-159.
The provision of the emitter follower output circuit presents such advantages as increased driving ability while enabling a wired-or circuit to be constructed. On the other hand, it presents such defects as increased delay time (usually from 0.2 to 0.3 nanoseconds) due to the emitter follower circuit, increased power consumption, and an increased number of elements for constituting the circuit.
When the emitter follower output circuit is eliminated, on the other hand, the circuit operates at high speeds while consuming less electric power. For relatively heavy loads having a large number of fan outs, however, the circuit cannot operate at high speeds since its driving ability is small, and it also becomes difficult to constitute wired-or circuits.
In designing the control logic circuits (random logic circuits) consisting of gate circuits, logic arithmetic circuits, shift registers, and the like, the inventor of the present application has contrived to exploit the features of the above-mentioned two types of ECL circuits or to use the ECL circuit of either type depending upon heavy loads and light loads. Namely, the ECL circuit without the emitter follower output circuit shown in FIG. 1 is used for the circuits for driving relatively light loads so that the operation can be carried out at high speeds under light load conditions, and the ECL circuit having the emitter follower output circuit shown in FIG. 2 is used for the circuits for driving relatively heavy loads or for the circuits which perform the wired-or function.
In the ECL circuit shown in FIG. 1, however, a reference voltage V.sub.B is set to be, for example, -0.3 V, the high level of the input voltage IN is set to be 0 V, and the low level of the input voltage IN is set to be about -0.6 V. In the ECL circuit shown in FIG. 2, on the other hand, the reference voltage V.sub.B is set to be -1.1 V, the high level of the input voltage IN is set to be -0.8 V, and the low level of the input voltage IN is set to be about 31 1.4 V. When the signals are to be delivered and received between the ECL circuit of FIG. 1 and the ECL circuit of FIG. 2, however, it becomes necessary to provide a level converting circuit. The level converting circuit, however, makes it difficult to maintain high-speed operation, to simplify the circuit setup or to reduce the consumption of electric power. Furthermore, in designing the logic circuits, the difference in the signal levels must be taken into consideration; i.e., the level converting circuit makes the design complicated. Moreover, it is necessary to provide two circuits for generating the reference voltage V.sub.B.
From the foregoing facts, it was clarified that a complex logic circuit made up of the combination of the ECL circuit of FIG. 1 and the ECL circuit of FIG. 2, is not so superior to the case when a complex logic circuit is constructed by using the ECL circuit of FIG. 1 alone or by using the ECL circuit of FIG. 2 alone in a customary manner.